Chapter 2

 

Operational Amplifiers

 

Gordon W. Roberts 

Department of Electrical & Computer Engineering, McGill University

 

 

Having just been introduced to several aspects of circuit simulation using Spice, we are now ready to re-enforce our understanding of linear circuits constructed with Operational Amplifiers.  We shall begin our investigation by developing a simple voltage-controlled voltage-source (VCVS) representation of the op amp from which to study various types of op amp circuits.  Progressively, we shall increase the complexity of the op amp model in order to capture more of the true-life behavior and the effect that this behavior has on closed-loop circuit operation.  Several new Spice concepts will be discussed here; largely in order to describe the nonlinear circuit behavior of an op amp to Spice.  

2.1 Modeling an Ideal Op Amp with Spice

 

An ideal op amp as shown in Fig. 2.1 may be modeled as a voltage-controlled voltage source with infinite voltage gain (i.e.,  A ® ¥).  The input resistance is very high, infinite in fact, and the output resistance is considered to be zero since the output node is driven directly by a voltage source.  Moreover, the voltage gain is assumed to be independent of frequency.  At a first glance, a Spice model for the ideal op amp may seem to be trivial - a one-line VCVS Spice statement. Unfortunately, Spice has no concept of infinity, hence, the infinite voltage gain cannot be specified as a Spice value.  Instead, we must compromise the accuracy of our ideal model by specifying a large, but finite, voltage gain value.  Normally, a value of 10⁶ V/V is sufficient without any significant deviation from the ideal. Under this gain condition, we shall consider the op amp as pseudo-ideal.

 

 

 

2.2 Analyzing the Behavior of Ideal Op Amp Circuits

 

We have now come to a point where we can use Spice to analyze the behavior of various types of op amp circuits, and thus develop a better understanding of these circuits.

 

2.2.1 Inverting Amplifier

 

Consider the inverting op amp circuit shown in Fig.  2.2(a) which consists of one ideal op amp and two resistors R₁ and R₂.  We would like to determine the DC transfer function of this circuit when R₁ and R₂ assume values of 1 kΩ and 10 kΩ, respectively.

 

To perform this calculation using Spice we shall make use of the Transfer Function (.TF) command briefly discussed in the last chapter. The syntax of this command was not discussed there, rather we shall present it here and use it to analyze the op amp circuit shown in Fig. 2.2(a).

  

The transfer-function analysis command of Spice computes the DC small-signal gain from the input of a circuit driven by some signal source to some pre-specified network variable. In addition, this command will also calculate the input resistance of the circuit as seen by the input source, and the output resistance seen looking back into the circuit from the port formed by the output variable and ground. Alternatively, this command can be viewed as calculating the Thevenin or Norton equivalent circuit of the network from the point-of-view of the input and output ports.

 

 

 

A general description of the syntax of the Transfer Function analysis command (.TF) is given in Table 2.1. The different fields of this command should be self-evident from the discussion above. The command line begins with the keyword .TF followed by the output variable, either a voltage at a node or a current through a resistor or voltage source, and the name of the input signal source for which the output will be referenced to. The results of the .TF command are accessed using the waveform viewer by displaying the following three parameters containing the words: input_impedance, output_impedance and Transfer_function.  There will be some additional letters appended to these words.  These correspond to the output variable and input source name.

 

Returning to the circuit shown in Fig.  2.2(a), it is captured in LTSpice using its drawing capabilities.  Note the input and output nodes are labels as IN and OUT, as well the remaining node is labeled as INV-.  A one-volt DC signal is applied to the input of the circuit and a .TF analysis request is included to compute its DC small-signal voltage gain. The op amp is modeled as a VCVS with a voltage gain of 10⁶ V/V The corresponding circuit netlist is listed in Fig. 2.3.  

 

The results of the Transfer Function analysis results in the following set of plots:

 

 

 

The voltage gain from the DC input source to the op amp output is -9.999 V/V, which is very close to -10 V/V, the expected voltage gain determined by the ratio - R₂ / R₁.  In addition, the input and output resistances are listed. Combining this information with that of the gain calculation allows us to represent the op amp circuit of Fig. 2.2(a) with the equivalent circuit model shown in Fig.  2.4.

 

 

 

 

 

 

2.2.2 The Miller Integrator

 

Our next example illustrates another important application of the inverting op amp configuration.  Consider replacing R₂ in the inverting amplifier circuit shown in Fig.  2.2 with a capacitor C₂.  The resulting configuration is known as the inverting or Miller integrator circuit and is shown in Fig.  2.5(a).  Here we wish to determine the transient response of a Miller integrator with R₁=1 kΩ and C₂=10 uF subject to a 1-volt step-input.  On completion of this, we would also like to determine its AC frequency response.

 

The schematic captured by LTSpice can be seen in Fig.  2.5(b) and the corresponding Spice netlist is shown listed in Fig. 2.6.  As before, an ideal VCVS with a gain of 10⁶ V/V is used to model the op-amp.   An ideal step function does not exist in Spice, so we need to approximate the step function with a series of piece-wise linear segments using the PWL signal type.  The pulse is held low at 0 V for 1 ms and then made to rise to 1 V with a rise-time of 1 us, and then held at 1 V for 9 ms.  If the rise time of this pulse was made equal to zero then we would have realized a step function exactly; unfortunately, LTSpice will not accept a waveform having a rise-time of zero.  Alternatively, we could decrease the rise time of the step input and more closely approximate the step function; however, this only increases the time to complete a simulation.  For this particular example, a rise-time of 1 us was found to be sufficient. Once the signal attributes have been set, the element statement found in the circuit netlist should appear as

 

V1 IN 0 PWL(0 0V 1ms 0V 1.001ms 1V 10ms 1V)

 

The results of the transient simulation are shown in Fig.  2.7. The top curve represents the input step signal and the bottom curve represents the output of the integrator.  As is clearly evident, the output signal is the time-integral of the input signal, i.e., the integral of a step function is a ramp function.  The rate at which the ramp output decreases is -400 mV/4 ms or -100 V/s.  The magnitude of this rate can easily be shown to be equal to V_I/C₂R₁ where V_I is the magnitude of the input step. It should then be obvious why this circuit is called an integrator.

 

It is also interesting to observe the magnitude response behavior of the two damped integrators as a function of frequency and compare it to that obtained for the Miller integrator.  Consider modifying the input signal source V1 with a small-signal AC value. You do not have to change the source from a PWL signal type, as all the signal types have the option of including an AC value.  Right-click on voltage source V1 and the source attribute table will appear.  About halfway down, you will see a Small-Signal Parameters (.AC) heading.  Below this, set the AC Amplitude to 1 V and the AC phase to 0 degrees. Always use 1 V as the AC amplitude so that the magnitude of the output AC response represents the magnitude of the transfer function.   Once the changes are made, the element statement found in the circuit netlist should now appear as

 

V1 IN 0 PWL(0 0V 1ms 0V 1.001ms 1V 10ms 1V) AC 1 0

 

In addition, we replace the .TRAN statement by an .AC statement specifying the range of frequencies that we are interested in.  For this particular case, we are interested in a fairly broad frequency range of 1 Hz to 1 kHz, thus we decided to use a log sweep of the input frequency by including the following .AC analysis statement on the schematic of Fig. 2.5(b).

 

.AC DEC 5 1Hz 1kHz.

 

It is important to note that only one Spice directive can be active at a time.  In this case, we toggle the .TRAN statement to a comment and made the .AC statement a Spice directive. There is a color change between the two statements to signify that one is a comment, the other a Spice directive.  Which color you see with your LTSpice will depend on your color mappings.  The setting here, a blue text signifies a comment and black text signifies a Spice directive. 

 

The AC frequency response of the Miller integrator as calculated by LTSpice is displayed in Fig. 2.8. The magnitude of the output node voltage expressed in dBs (V(out)) is large at low frequencies and rolls-off at a rate of -20 dB for each decade increase in frequency. Using the Waveform Viewer, we find that the frequency at which the magnitude of the output voltage crosses the 0-dB level is 15.9 Hz. This corresponds exactly with the result of substituting the circuit parameters into the expression 1/ (2p R₁C₂).

 

 

 

 

 

 

2.2.3 A Damped Miller Integrator

 

The DC instability of a Miller integrator is a result of the very high (ideally infinite) DC gain that the Miller integrator has. The DC gain can be made finite by connecting a feedback resistor across integrating capacitor C_2, as shown in Fig. 2.9(a). Unfortunately, however, this makes the integrator nonideal. It is commonly referred to as a damped integrator. To obtain near ideal response over a large frequency range the feedback resistor should be as large as possible.

 

In the following we shall investigate the behavior of a damped integrator for two different-sized feedback resistors. Specifically, we shall compare the step response of a damped integrator with feedback resistors of 100 kΩ and 1 MΩ to that of an ideal integrator. On doing so, one will also learn about how to be connected multiple circuits to a single source using node labels.  The schematic capture of this circuit combination is shown in Fig. 2.10. The top circuit is the ideal Miller integrator, the middle and bottom circuits are damped integrators with 1 MΩ and 100 kΩ feedback resistors.   Here all three integrator circuits are driven from the same source V1.  Rather than physically draw a wire from the source to the inputs of all three integrators, a more convenient way is to label the source node as shown here with label “IN” (for input) and create two more identical labels and place them on the input node of each integrator.  On doing so, all three integrators are connected together.  The use of labels can simplify the presentation of any schematic circuit. However, a very important downside of the application of label is that when one duplicates a circuit or a portion of a circuit, the node label does not change unlike the name for any Spice element like a resistor.  As a result, the two circuits are actually connected together via the label “IN”.  BE VERY CAREFUL WITH LABELS! 

 

The amplitude of the input step is reduced to 1 mV from the original 1-V level used in the previous Miller integrator simulation.  This is necessary to keep the output signal level within practical limits (i.e., between typical power supply levels). The PWL source was modified with the following

 

Vi 3 0 PWL (0 0V 1ms 0V 1.001ms 1mV 2s 1mV).

 

As the final change, the transient analysis command statement is changed from the previous case to read as follows:

 

.TRAN 100ms 2s 0s 100ms.

 

The results of the transient analysis are displayed in Fig. 2.12.  All three integrator outputs are superimposed on the same plot. Up to about 0.1 s, all three step responses are almost identical. After this, the integrator that is damped with 100 kΩ begins to deviate from the other two. Moreover, as the time progresses, the curve corresponding to this one begins to settle towards -100 mV. In the case of the 1 MΩ damped integrator, similar behavior is also observed but with a different time scale. The step response of this integrator begins to significantly deviate from the ideal after about 1 s. Although not shown, if we were to have the transient response analysis run longer, we would see the step response of this integrator settle to a -1 V level.  In either of the two damped integrator cases, we see that the step response deviates significantly from the ideal situation in about one-tenth the time-constant formed by the integrating capacitor C₂ and the damping resistor R₂ (i.e., C₂R₂/10). We can therefore conclude that the output of a damped integrator behaves much like an ideal integrator for times less than one-tenth the time constant formed by the feedback capacitor and resistor.

 

It is also interesting to observe the magnitude response behavior of the two damped integrators as a function of frequency and compare it to that obtained for the Miller integrator.  Consider modifying the input signal source V1 to include a small-signal AC amplitude of 1 V and a 0-degree phase shift. Once the changes are made, the element statement found in the circuit netlist should appear as

 

V1 IN 0 PWL(0 0V 1ms 0V 1.001ms 1mV 2s 1mV) AC 1 0

 

Also change the spice directive to sweep the AC response from 1 mHz to 1 kHz using 5 points per decade as follows:

 

.AC DEC 5 1mHz 1kHz.

 

On completion of the AC analysis, we obtain the results shown in Fig. 2.13. In contrast to the results of the ideal integrator, the two damped integrators have a magnitude response that consists of two parts: A low frequency component that is essentially independent of frequency and a second component that rolls off linearly with frequency at a rate of -20 dB/dec. The frequency point that divides the two regions is approximately the reciprocal of the time-constant formed by the feedback resistor and capacitor (i.e., 1/(2pC₂R₂)). For frequencies about ten-times larger than the corresponding break or 3 dB frequency of the damped integrator, both the ideal and the damped integrator have essentially identical frequency response behavior. Thus, for input signal frequencies larger than 10 times the 3-dB frequency of the damped integrator, the response of the damped integrator closely approximates that of the ideal Miller integrator.

 

 

 

 

There is another way in which to analyze a circuit whose topology is the same, but the component values may be different. This involves the Spice directive called .STEP.  This command causes an analysis to be repeatedly performed while stepping the temperature, a model parameter, a global parameter, or an independent source. Steps may be linear, logarithmic, or specified as a list of values.  A summary of some of the ways in which to invoke the .STEP command is listed in Table 2.2.  The first three .STEP commands suggest that the temperature or circuit variable (voltage or current) or model parameter of the circuit can be swept from a start value to an end value with a predefined increment. The last two .STEP commands involves defining a variable between brackets { } and varying this parameter from a start value to an end value with a predefined increment, or one can define a list of values for the variable to be assigned. Further details can be found with the on-line help feature of LTSpice. 

 

To illustrate the application of a .STEP directive, consider the damped integrator shown in Fig. 2.14.  Here the value of the feedback resistor R2 is assigned a parameter {R_value}. The brackets are necessary to execute the parameter assignment before simulation.  The Spice directive seen at the bottom of Fig. 2.14, and repeated below

 

.step param R_value LIST 1000Meg 1Meg 100k

 

tells LTSpice to repeat the AC analysis by assigning the feedback resistor R2 to three separate values 1000 MΩ, 1 MΩ and 100 kΩ. While the latter two values are identical to the values used in the previous example, the first value of 1000 MΩ is meant to approach the ideal integrator situation.  While it is not ideal, a value of 1000 MΩ certainly approaches an open circuit condition.  The results of this analysis are seen in Fig. 2.15.  As is evident, the AC results are identical to the results seen in Fig. 2.13 where independent circuits were used for each feedback resistor value.

 

 

 

 

2.2.4 Instrumentation Amplifier

 

Our next example is a two-stage instrumentation amplifier shown in Fig.  2.16 consisting of three op amps.  Such an amplifier is usually employed as the front-end of an instrument that measures a differential signal between the amplifier input terminals (e.g., 20 mV in Fig. 2.16). We would like to investigate the effect of a 60 Hz common-mode signal on such a measurement, as shown in Fig. 2.15.  Each op-amp will be assumed ideal (as before, modelled as a VCVS with a gain of 10⁶ V/V). 

 

On performing a transient analysis over five cycles of the common-mode signal, one observes in Fig. 2.18 that the voltage waveform appearing at the output of the instrumentation amplifier is a constant DC signal of about 420 mV, even though the voltage appearing at the inputs of the instrumentation amplifier (nodes IN1 and IN3) are time-varying voltage waveforms riding on the very small DC signal of 10 mV. Comparing the DC level found at the output with that predicted by the following equation for the instrumentation amplifier with the matching constraint R₂=R₃, R₄=R₅ and R₆=R₇,

one finds that the simulation results confirm the theorical results. Moreover, the theory also predicts that the 60 Hz common-mode signal will not appear at the output. This highlights an important feature of the instrumentation amplifier; its ability to reject common-mode signals while amplifying much smaller difference signals.

 

In the above simulation we assumed that the appropriate pairs of resistors (R₄, R₅, R₆ and R₇) were perfectly matched.  In practise, this is rarely the case and, as a result, the lack of matching will affect the common-mode rejection capability of the instrumentation amplifier.  To illustrate this, consider altering one of the resistors of the difference amplifier, say R₅, by 1% of its nominal value.  In other words, we shall repeat the above simulation with R₅ having a value of 10.1 kΩ. On doing so, one finds at the output of the instrumentation amplifier a 250-mV peak-to-peak 60 Hz frequency component riding on a DC level of 420 mV.  The actual simulation result for the output waveform is displayed in Fig. 2.19.  Clearly, the common-mode signal is now present at the output. This illustrates the importance of having closely matched resistors in the difference amplifier portion of the instrumentation amplifier. 

 

 

 

 

 

 

2.3 Nonideal Op Amp Performance

 

In previous sections we performed several LTSpice simulations assuming that the op amps used had a very large open loop gain and that the gain was independent of frequency.  In the remainder of this chapter we shall incorporate more of the nonidealities of practical monolithic op amps into our simulations; thus, obtaining results that are more realistic of closed-loop op amp behavior.  As some op-amp models can be very complex, the concept of a subcircuit is often used. Let’s us begin by describing the concept of a subcircuit.

 

2.3.1 Using Subcircuits In LTSpice

 

To provide circuit hierarchy, the Spice Description Language (SDL) includes the concept of a subcricuit in much the same manner that a software language such as the C or C+ language provides hierarchy through the introduction of a sub-routine, procedure or subprogram. A subcircuit is considered separate and isolated from the main circuitry except that it is connected to the main circuit through specific nodes.  Such a subcircuit can, of course, be used repeatedly in the same main circuit. Experience has shown that LTSpice input files are easier to read, and simpler to debug, when a large circuit is described using subcircuits. In addition, once a subcircuit is created for a specific building block, it can be re-used by other circuits constructed from the same building blocks. Thus, subcircuits provide a convenient way of creating a library of basic building blocks for future use. In fact, this is one of the main reason ADI distributes such a powerful simulation tool (LTSpice) so that it can promote its product line.

 

The format and syntax of a subcircuit definition is displayed in Fig.  2.20.  It begins by a .SUBCKT statement followed by a unique name and a list of the internal nodes of the subcircuit that will be allowed to connect to the main circuit. Subsequent statements are used to describe the subcircuit to LTSpice in exactly the same way as that performed for the main circuit.  The nodes of the subcircuit are local to the subcircuit and can have the same name or label as those used in the main circuit or any other subcircuit.  One exception is the ground node (node 0) which is common to all circuits; the reason it is referred to as a global parameter.  Similarly, the names of the elements making up the subcircuit are also local to the subcircuit and can be the same as those used for other elements in the main circuit. To conclude the definition of the subcircuit, the final statement must be an .ENDS statement.  Notice that this includes an ``S'' appended on its end to distinguish it from an end to the Spice input file.  The name of the subcircuit may also be included on the same .ENDS statement to clearly mark the end of the subcircuit.

 

Once a subcircuit has been defined it can be incorporated into the main circuit in much the same way as any other circuit element is described in SDL.  The beginning of the statement is a unique alphanumeric name prefixed with the letter ``X'' followed by a list of the nodes of the subcircuit that connect it to the main circuit.  The third field specify the name of the subcircuit that is being referenced.  Obviously, there must be a one-to-one correspondence between the list of nodes given on this statement and the ones listed on the .SUBCKT statement.  There is also an optional forth field that allows for parameters to be passed between the main circuit description and the subcircuit. More on this in a moment. For quick reference, the syntax of this statement is displayed in Table 2.3.

 

As a simple example, consider replacing the op-amp in the inverting amplifier circuit of Fig. 2.2 using a subcircuit.  The most direct way in LTSpice is to select an op-amp component from the list of op-amps found in the component library, in much the same way as a resistor or capacitor was selected. As we are looking for a three-terminal op-amp, one that does not include power terminals, one scrolls down the list to the subcircuit titled ``opamp.’’ Click on it and a three-terminal op-amp will appear on the schematic circuit windowpane. Drop in in the appropriate place and connect to the rest of the circuit, as shown in Fig. 2.21.   Next, bring up the attributes of the op-amp (right click button) and change the field named Value from opamp to my_opamp.   You can delete the values in the fields corresponding to SpiceLine and SpiceLine2. A summary of all the edits can be seen in Fig. 2.22.  Next, the subcircuit corresponding to my_opamp must be created.  Using the VCVS model shown in Fig. 2.1, the following subcircuit was written by following the syntax seen described in Fig. 2.20:

 

 

The inputs to the op-amp was labeled as in- and in+, and the output as out.  The order of these node names is important and were defined when the symbol for the op-amp subcircuit was created. The node names are unique to the subcircuit and have no relationship to other nodes label as in or out in the main circuit.  A statement for the VCVS having a gain of 10⁶ V/V is also provided.  This text is then entered onto the schematic pane by copy and pasting into a Spice directive command.  The result can be seen in the lower right-hand portion of the schematic view shown in Fig. 2.21. The corresponding circuit netlist generated by LTSpice with a few edits for clarity can be seen listed in Fig. 2.23. Simulating the circuit results in the response shown in Fig. 2.24.

 

 

 

 

 

LTSpice provides another method in which to incorporate the hierarchy approach enabled by subcircuits.  By saving the subcircuit description in a text file, the file can be included into a LTSpice simulation by using the Spice directive command .include or, one can write .inc.  The syntax of this command is summarized in Table 2.4.  Here the path and full name of the file (with suffix) points to the appropriate subcircuit file.  For instance, the subcircuit described above for my_opamp was typed into a text file and saved in a file as my_opamp.sub.   The suffix .sub indicates it is a subcircuit file.  One can also use the suffix .cir to confirm with files created with other Spice programs such as PSpice.  To keep the folder from too much clutter, the file was moved into a local directory called ch2_library.  The my_opamp subcircuit description seen listed in Fig. 2.21 was replaced by the following Spice directive:

 

.inc ch2_library/my_opamp.sub

 

The schematic capture window will appear as that shown in Fig. 2.25 and the corresponding circuit netlist is listed in Fig. 2.26.  Here the netlist does not include the SDL for the subcircuit rather provides a pointer to the file.  The .include directive enables files from anyone or any company to be incorporated into a LTSpice simulation.  There is another method in LTSpice that uses the built-in subcircuit library.  This will be described in the next subsection.

 

 

 

 

 

 

2.3.1 Small-Signal Frequency Response of Op Amp Circuits

 

Op amp nonidealities can be incorporated into the op amp circuit model in various ways.  One method involves constructing a circuit whose terminal behavior provides a close resemblance to actual op amp terminal behavior. Obviously, one tries to find a simple circuit that captures the op amp nonideal behavior.  For the small-signal performance, we shall use a lumped circuit model (an equivalent circuit) to represent the frequency response of the op amp. The differential small-signal open-loop gain of an internally compensated op amp can be mathematically described as

(2.1)

 

where A₀ denotes the DC gain and w_b is the 3-dB break frequency.  Typically, A₀ is very large, on the order of 10⁶ V/V for modern bipolar op amps such as the 741 op-amp and w_b typically ranges between 1 and 100 rad/sec.  The single-capacitor circuit shown in Fig. 2.21 has infinite input resistance and zero output resistance, much like the ideal op amp, and it can be shown that it has the following single-pole transfer function:

(2.2)

 

Clearly, if we let G_mR₁ = A₀ and R₁C₁ = 1/w_b, then the circuit shown in Fig.  2.27(a) can be used to model the small-signal frequency response of the op amp in LTSpice.  As an example, consider typical frequency response parameters for the 741 op-amp: it has a DC gain of 2.52 x 10⁵ V/V and a 3 dB frequency of 4 Hz. Using the above equations, we can write two equations in terms of three unknowns.  Thus, we have at our disposal a single degree of freedom which we can exercise to obtain the other two circuit parameters. That is, if we let C=30 pF then we can solve for G_m= 0.190 mA/V and R₁= 1.323 x 10⁹ W.  The corresponding subcircuit netlist would appear as that shown listed in Fig. 2.27(b). LTSpice allows parameter values to be passed between the main circuit description and a subcircuit in much the same way parameter values are passed between a subroutine and the main routine in a computer language. By parametrizing the values for the circuit components C, Gm and R, values can be passed to the subcircuit. This provides greater subcircuit flexibility. To pass a value between the main circuit and a subcircuit, three things must be done: (1) define a variable in the main circuit description using the Spice directive .PARAM, (2) list the parameter values on the subcircuit call statement, and (3) pass the parameter values to the subcircuit by referencing these variables enclosed by brackets { }.  The brackets force a substitution/calculation before a simulation otherwise an error may result.  In so far as how the subcircuit is written with parameter passing, Fig. 2.27(c) illustrates the use of the variable declaration for C, Gm and R parameters.  The parameter defining statement would then appear in the main circuit description as

 

.PARAM C=30p Gm=0.190m R=1323M

 

and the subcircuit calling statement would appear as

XU1 INV- 0 OUT small_signal_opamp C_op=C Gm_op=Gm R_op=R

 

It is imperative that one check that the op amp model behaves as expected otherwise false conclusions would later be drawn.  We shall perform this check in conjunction with our next example where we investigate the effects that the limited op amp gain and bandwidth have on the closed-loop gain of an inverting amplifier.

 

Consider calculating the frequency response of the inverting amplifier shown in Fig.  2.2 for nominal gains of -1, -10, -100 and -1000 using the one-pole op amp model calculated above. Furthermore, we will want to contrast the frequency response obtained in these four closed-loop cases with the open-loop response of the op amp through a .STEP directive. The open-loop response is approached through a very large feedback resistor (1000Meg Ω). The circuit schematic captured by LTSpice is shown in Fig. 2.28 and the corresponding netlist is shown in Fig. 2.29.   The frequency response behavior of the inverting amplifier under different gain settings is displayed in Fig.  2.30 together with the op amp open loop frequency response.  One sees clearly the effect of increasing amplifier gain on its bandwidth.  Moreover, the gain and bandwidth are seen not to exceed those values of the open-loop frequency response.

 

 

 

2.3.2 Modeling the Large-Signal Behavior of Op Amps

 

Alternatively, terminal behavior can be specified using a mathematical expression in either functional or piecewise-linear form which has come to be known as analog behavior modeling.  Such an approach forms a very elegant and powerful means of specifying nonlinear circuit behavior.  We shall utilize this approach below to investigate the effect of large-signal properties of an op amp on the closed-loop response of op amp circuits.

 

The above subcircuit model for the op amp is limited to circuit situations where the output voltage of the op amp is small.  In this section we shall elaborate on the op amp subcircuit so that it can be used to model op amp behavior when subjected to both small and large input signals.  To accomplish this, consider that the internal structure of an actual op amp consists of three parts as shown in Fig. 2.31 in contrast to the single stage model put forth above in the last subsection.  The front-end stage consists of a differential-input transconductance amplifier, followed by a high gain voltage amplifier with gain -u (mu), together with a feedback compensation capacitor C, and the final stage is simply an output unity-gain buffer providing a low output resistance.  By modeling the terminal behavior of each stage of the op amp, accommodating both linear and nonlinear behavior, realistic op amp characteristics can be captured by Spice without simulating detailed internal circuitry.

 

To describe the behavior of these three stages to Spice, we make use of the equivalent circuit shown in Fig.  2.32.  Here the gain of each dependent sources is expressed as an unspecified function of the controlling signal.  The gains of these stages are written this way in order to convey to the reader that both the linear and nonlinear behavior of each of the internal stages is to be captured by these dependent sources. Spice has provisions for specifying nonlinear dependent sources; however, the functional description must be expressible in polynomial form. Unfortunately, this makes specifying arbitrary functions difficult. Instead, newer versions of Spice, such as LTSpice, allow users to specify the control function as a mathematical expression or in piecewise-linear form. We shall elaborate on this further below.

 

 

Limited Current-Output of The Front-End Transconductance Stage

 

The first stage of an op amp is a circuit that converts a differential input voltage signal into a corresponding current.  The operation of this stage is largely linear with transconductance G_m; however, the maximum output current that it can source, or sink, is limited to a value I_max. Conversely, the transconductance stage will behave linearly provided the input voltage levels are restricted to lie within the range -I_max/G_m to I_max/G_m.  To help the reader visualize these transfer characteristics we display them in Fig. 2.33.  Now, to try and capture this behavior with a set of polynomials would be very difficult, if not, impossible.  Instead, it can be very easily incorporated into the circuit representation using the analog behavior modeling capability of LTSpice. 

 

The analog behavior model feature of LSpice is a set of extensions made to the VCVS and VCCS statements.  These extensions allow the user to specify the controlled signal (voltage or current) in terms of the controlling variable (again, voltage or current) as either a mathematical expression or in piecewise-linear form.  For example, the level of a VCCS with its output terminals connected between node 4 and ground, and the controlling nodes between 2 and 3 can be made dependent on the square of the controlling node voltages by simply using the following LTSpice description,

 

Gsquare 4 0 VALUE = { V(2,3)*V(2,3) }.

 

The first three fields of this VCCS statement is like before; a unique name beginning with the letter G, followed by the nodes that the current source output is connected to.  The subsequent fields are the extensions that we made reference to above.  The keyword VALUE indicates to LTSpice that this VCCS has a functional description defined by the field enclosed by the braces { } found after the equal sign.  In this particular case, the functional description is the product of the voltage between nodes 2 and 3 with itself. In general, the functional description consists of an arithmetic expression in terms of the network variables and arbitrary constants.  The arithmetic operators allowable are +, -, * and /.  Parenthesis may also be used to simplify the notation.  In addition, functions can also be included in each expression; however, this is beyond the scope of this text.  Interested readers can consult the on-line LTSpice Help Manual for more details.

 

Another extension to the LTSpice voltage-controlled source statement is one that allows the transfer function characteristics of the dependent source to be described in terms of a table of values.  For example, the transfer characteristics of the input transconductance amplifier of the op amp, shown in Fig.  2.33, is simply described using the following LTSpice statement:

 

Ginput 4 0 2 3 TABLE = ( -Imax/Gm -Imax , +Imax/Gm +Imax )

 

The first three fields of this statement should be obvious at this point from the above discussion.  The keyword TABLE indicates that the controlled source has a tabular description. The value of the controlled source is specified by the table of ordered pairs on the right-hand side of the expression. The output values corresponding to input values that fall between specified points are computed by linearly interpolating between them.  Thus, one can view the table of ordered pairs as points interconnected by straight lines. Thus, in the above case, a straight line having a slope of G_m interconnects the points: (-I_max/G_m, -I_max) and (+I_max/G_m, +I_max).  The output value corresponding to an input that falls outside the limits of the table is considered to be equal to the output value corresponding to the smallest (or largest) specified input, thus forming the two saturating limits of the amplifier.

 

Output Saturation

 

Op amps behave linearly over a limited range of output voltages, usually bounded by the voltage levels of the power supplies.  In a similar manner to the input transconductance stage above, we can specify some piecewise-linear function for the voltage gain of either the middle-stage voltage amplifier or the output buffer, or both.  An example of this will be given below under the subsection entitled:  A LTSpice large-Signal Op Amp Subcircuit.

 

Frequency Response

 

Within the linear region of the equivalent circuit devised for the op amp in Fig. 2.32 (i.e., i(v_id)=G_m v_id, v(v_i2)= u v_i2, and v(v_o2)=v_o2 ) one can show that the input-output transfer function is given by

(2.3)

 

One can then draw a comparison between this equation and the one-pole model of the frequency response for the op amp given in Eq. (2.1) and deduce the following: A₀ = u G_m R and w_b = 1 / C ( 1 + u) R.  Multiplying these together results in the gain-bandwidth product w_t given by

(2.4)

Since, usually u >> 1, one can write

 (2.5)

 

A LTSpice Large-Signal Op Amp Subcircuit

 

Combining the nonlinear effects described above, together with the op amp limited frequency response behavior, we can create a subcircuit description for the op amp that is valid under both large and small signal conditions. Of course, we shall make use of the op amp equivalent circuit shown in Fig. 2.32.

 

Consider an op amp characterized by a DC gain of 2.52 x 10⁵ V/V, a unity-gain frequency of 1 MHz, and a slew-rate of 0.633 V/us. Furthermore, we shall assume that the internal compensation capacitor C is 30 pF and that the op amp output stage saturates at ±10 V. As the slew-rate of an op amp is related to the transconductance stage current limit I_max and the capacitor C according to

 (2.6) 

 

Thus, for this particular op amp example, I_max is limited to 19 uA.  Likewise, the transconductance of the first stage is simply deduced from Eqn. (2.5) above to be 0.19 mA/V. The remaining two parameters u and R are now left to be determined. Unfortunately, they cannot be uniquely determined from the information provided. We shall instead assume R=2.5 x 10⁶ W and derive u from A₀= u G_m R to get u= 529 V/V.

 

A subcircuit capable of capturing both the small- and large-signal behavior of the op amp described above is listed below (refer to Fig. 2.32):

  

2.4 The Effects of Op Amp Large-Signal Nonidealities On Closed-Loop Behavior

 

Now that we have created a subcircuit for the op amp that accounts for several of its nonidealities, let us explore some of the idiosyncrasies of the op amp in various closed-loop configurations.

 

 

 

 

 

2.4.1 DC Transfer Characteristic of An Inverting Amplifier

 

Consider the inverting amplifier circuit first shown in Fig.  2.2 with resistors R₁=1 kΩ and R₂=10 kΩ. Let us calculate the DC transfer characteristic of this circuit using LTSpice assuming that the op amp is nonideal and modeled as described above in the last section for large signal operation as shown in Fig. 2.34(a).  The LTSpice input file is given in Fig.  2.34(b).

 

The results of the DC sweep calculations are displayed in Fig.  2.35.  As can be seen from this graph, input signals of magnitude less than 1 V will experience a signal gain of -10 without distortion as inferred from the slope of the line in this region.  Whereas, signal amplitudes exceeding this limit will not be amplified, but instead the output will be held at a constant voltage of ±10 V depending on the sign of the input signal.  Thus, linear circuit operation is limited to input signals less than a volt in magnitude.

 

To see how these transfer characteristics manifest themselves in the time-domain consider applying a sinewave of 400 mV peak amplitude at a 1 kHz frequency to the input of the amplifier and then repeat the same analysis using an input signal that has a signal amplitude larger than the 1-volt limit.  In this particular case, we shall use a signal level of 1.1 V peak.   The source amplitude was replaces with a variable {Vamp} using the source attribute editor and will be changed from 400 mV to 1100 mV using the following step command:

 

.STEP param Vamp LIST 400mV 1100mV

The DC sweep directive was also changed to the following transient analysis command:

 

.TRAN 10u 5ms 0s 10u.

 

The results of these two transient analyses are shown in Fig.  2.36.  Clearly, when the input level exceeds the 1 V limit, the output signal becomes clipped.  Whereas, the other signal is amplified without any distortion.

 

 

 

 

 

 

2.4.2 Slew-Rate Limiting

 

Another important phenomenon caused by internal amplifier saturation effects is that of slew-rate limiting. This effect plays an important role in determining the high-frequency operation of op amp circuits. To obtain a better understanding of this effect, let us simulate a commonly used experimental set-up for characterizing op amp slewing. This set-up consists of an op amp in a unity-gain configuration and a generator supplying a voltage step as an input signal, as shown in Fig. 2.37(a). We shall use exactly the same large-signal op amp subcircuit developed in the last section; however, we shall add additional terminals to the op amp subcircuit so that we may monitor the output current of the first stage as shown in Fig. 2.37(b). As we shall see, op amp slew-rate behavior is fully explained by the behavior of this current.  The symbol for this 5-terminal op-amp was taken from the opamp2 subcircuit found in the LTSpice library of op-amps.

  

For the first part of our simulation, consider applying a very small step input of 1 mV and observe the transient response at the output of the amplifier and the current that flows between the first and second stages.  The LTSpice netlist is listed in Fig. 2.37(c).   The results of this analysis are displayed in Fig. 2.38(a).  The top curve of Fig. 2.38(a) displays both the step input voltage signal and the corresponding output response, the curve below it represents the voltage appearing between the input terminals of the amplifier, and the bottom curve represents the output current of the first stage. As is evident, the output voltage signal increases towards its final state in an exponential manner. Similarly, the voltage appearing between the input terminals of amplifier and the output current of the first stage follows a similar exponential pattern. Moreover, we see that these two signals are proportional to one another; albeit with a negative sign.  These results are expected of an op amp whose dynamic behavior is modeled as a single-time-constant network.

 

Conversely, if a 1 V step input is applied to the input terminal, then instead of an exponential increase in the output voltage, the output voltage ramps up at a constant rate as shown in the top graph of Fig.  2.38(b).  This rate, of course, is the slew-rate of the op amp at 0.633 V/us.  To help understand this effect, refer to the voltage and current waveforms shown in the two graphs below the top one.  We see from the graph of the current waveform (bottom-most graph) that, for the most part, it is saturated at a constant level of -19 uA, which, of course, is the maximum current deliverable by the first stage i.e.  I_max.  It is not before the voltage between the input terminals of the op amp (middle graph) goes between ±I_max/G_m or ±100 mV does the transconductance stage enter its linear region and that the current generated by this stage begins to decrease at an exponential rate.

 

In terms of sinusoidal inputs, slew-rate limiting manifests itself in the output as a distorted sinewave. Consider applying a 100 kHz sinewave of 1.5 V amplitude to the input of the unity-gain buffer described above in the LTSpice input file listed in Fig. 2.37(c). This requires that one change the step input statement to a sinewave input using the following source statement:

 

Vi IN 0 SIN (0 1.5V 100kHz).

 

and change the transient analysis to the following

TRAN 10ns 50us 0s 10ns

 

The results of the LTSpice simulation are illustrated in Fig. 2.39. In addition to the input and output voltage waveforms, and the evidence of distortion in the output signal, the cause of this distortion should be clear from the waveform of the current signal delivered by the front-end transconductance stage. Under small-signal conditions, the current waveform is sinusoidal like the input, but, obviously, the front-end stage is being push beyond its linear capability and appears more square-wave like.

 

2.5 Other Op Amp Nonidealities

 

A practical op amp deviates from its ideal behavior in many other ways than those discussed previously.  Some of these additional nonidealities would include common-mode signal gain, finite input impedances, nonzero output impedance and, DC bias and offset signals.  In this section, we shall demonstrate how to incorporate these nonidealities into circuit simulation using Spice.

  

 

 

 

 

 

2.5.1 Common-Mode Gain

 

Accounting for op amp common-mode gain is accomplished by simply adding a dependent voltage source in series with the positive input terminal of the op amp, as shown in Fig. 2.40.  The op amp shown on the right-most side in Fig. 2.40 can be represented either by an ideal op amp model or one that captures more of its true-life small-signal and large-signal behavior. Assuming the op-amp is modeled as a VCVS with gain of 10⁶ V/V, the subcircuit netlist for an op-amp with common-mode gain would appear as:

 

As an example of common-mode signal error, we shall return to the instrumentation amplifier example discussed in section 2.2.4 and assume that the op amps have a finite common-mode rejection ratio (CMRR).  Recall that CMRR is defined as the ratio of the op amp differential gain to the corresponding common-mode gain.  The rest of the circuit will be assumed ideal and perfectly matched.  Thus, under ideal op amp conditions, common-mode signals appearing at the input of the instrumentation amplifiers should not appear at its output.  However, some common-mode signal will appear at the output and we wish to determine the magnitude of this signal when the op amps have an assumed CMRR of 80 dB and a finite DC gain of 120 dB.  The LTSpice captured schematic of the instrumentation amplifier using an op-amp subcircuit that accounts for common-mode gain is provided in Fig. 2.41.  The re-ordered circuit netlist as generated by LTSpice can be seen listed in Fig. 2.42.

 

The LTSpice results are shown in Fig. 2.43. The results show that a 2.5 mV 60 Hz signal component appears at the output.  Thus, this instrumentation amplifier has a common-mode voltage gain (A_CM) of 2.5 mV / 25 V, or 10^-4 V/V. Combining this with the result found previously for the differential gain (A_d) of 420 mV / 20 mV, or 21 V/V, we can compute the overall CMRR for this instrumentation amplifier to be 21 V/V / 10^-4 V/V or 106 dB.

 

 

Fig. 2.43: Common-mode signal feeding through from the input of the instrumentation amplifier to its output because of the finite CMRR of the op amp.

 

 

2.5.2 Input and Output Resistances

 

Input and output impedances can be added to the op amp subcircuit in a straightforward way. We encourage the reader to try and incorporate input and output resistors for the various op amp models presented above. On completion, calculate the input and output impedance of some closed-loop op amp circuit as a function of frequency. The results should prove interesting.

 

 

2.5.3 DC Problems

 

Consider the equivalent circuit for the op amp shown in Fig. 2.44 which is separated into two parts: the first part consists of a set of input-referred DC signal sources representing the offsets and bias currents of the op amp, and the second part consists of an op amp circuit free of any DC offsets or bias currents. The two current sources labeled I_B represent the average value of the DC current flowing into the op amp input terminals.  The polarity of these sources will depend on the front-end nature of the amplifier, i.e., positive for front-end npn transistors and negative for a pnp transistorized front-end.  The current source I_OS represents the difference between the actual currents that flow into the op amp input terminals.  The voltage source V_OS represents the input-referred offset voltage. A subcircuit taking into account these bias and offset signals is listed below:

 

Here we have specified that the op amp will have an input-referred offset voltage of +5 mV, an input bias current of 200 nA and an offset current of 5 nA. Notice that we are calling another op amp subcircuit named VCVS_opamp inside this new subcircuit. This form of nesting subcircuit calls is valid provided each subcircuit is found within the LTSpice netlist. But note that a subcircuit cannot be made to call itself.  The VCVS_opamp netlist would appear as follows:

 

Given the above model accounting for DC offset effects, let us consider the effect that these offsets have on integrator behavior.  Returning to the schematic for the Miller integrator shown in Fig. 2.5, we have modified it to include the above two described op amp model, as shown in Fig. 2.45. A transient analysis request is included in this file. An additional UIC (use initial conditions) flag is included on this analysis request in order to ensure that the transient analysis begins with all nodes in the integrator circuit at 0 V. Without UIC, the transient analysis would begin with the nodes set at their DC operating point which turns out to be the final conditions of the transient analysis. When calculating the transient behavior of a circuit that contains no time-varying voltage or current sources, a UIC command should always be included on the .TRAN statement. In this way, the DC operating point of the circuit will not be used as the initial condition for the circuit. The input to the integrator is set to zero in order for us to observe separately the effect of op amp offsets. The circuit netlist generated by LTSpice after re-ordering appears as that shown in Fig. 2.46.

 

 

 

  

The results of the transient analysis are shown in Fig. 2.37. We see here that even though the input to the integrator is zero, its output ramps upwards towards the positive power supply; clearly, an undesirable situation. In practise, one usually finds that eventually the op amp output voltage reaches the positive saturation level of the op amp.  We would not see this here since our op amp does not model output voltage saturation effects. But, of course, this could easily be included by replacing the ideal op amp model with one that accounts for op amp large-signal behavior, such as the one described in Section 2.3.2.

 

A practical method commonly used to eliminate this run-away effect is to connect a resistor across the integrator capacitor. Consider adding a 100 kW resistor across C₂ and re-run the transient analysis.  The voltage that appears at the integrator output is displayed in Fig. 2.38. Here we do not see the output voltage increase without bound, but rather, exponentially settle to a constant output signal of about 526 mV.  This is the net output offset voltage of the integrator.  This value can easily be calculated by hand analysis.

 

 

 

2.6 Chapter Summary

 

·      An ideal op amp can be modeled as a voltage-controlled voltage source with a large DC gain of at least 10⁶ V/V.

 

·      To simplify the schematic capture, subcircuits of basic building blocks of the main circuit can be used to separate different portions of the circuit into smaller, more manageable, circuit blocks.

 

·      Subcircuits can be nested to provided unlimited hierarchy.

 

·      LT Spice has the capability of describing the terminal behavior of a dependent source in either functional or piecewise-linear form. This is known as analog behavior modeling and provides a very elegant means of describing circuit behavior to Spice.

 

·      The initial conditions of a transient analysis can come from three sources: (1) DC operating point, (2) all node voltages and branch currents assumed 0, or (3) predefined initial conditions.  One should be aware of the initial conditions used by Spice during a transient analysis so that the results are meaningful.

 

·      As a general rule, when performing a transient analysis of a circuit that does not contain any time-varying sources, a UIC (use initial conditions) command should be included on a .TRAN statement.

 

·      Subcircuits can be nested to provided unlimited hierarchy.

 

2.7 LTSpice Tips

 

·      The DC operating point of a circuit is found using the Spice directive:

.OP

 

·      A DC transfer curve can be created using the following Spice directive:

.DC source_name start_value stop_value step-value

 

·      A small-signal AC analysis is performed using the following Spice directive:

 

.AC {LIN,OCT,DEC} points frequency_start frequency_stop

 

·      A small-signal transfer function analysis is performed using the following Spice directive:

 

.TF output_port input_source_name

 

·      A transient analysis is performed using the following Spice directive with initial condition:

 

.TRAN time_step time-stop no_print_time max_step_size

.IC V(node_1)=value V(node_2)=value ….

 

·      A circuit component can be assigned a parameterized value by identifying its value between brackets { parameter } and including the following Spice directive: 

 

.PARAM parameter = value

 

·      Any analysis can be repeated by specifying a range of values for a particular circuit variable using the following parameter sweep command:

 

.STEP circuit_varaible start_value stop_value increment_value

 

·      An alternative manner in which to perform an analysis can be repeated by first specifying a component with a parametric value x_value set between {x_value} and specifying a range of values for this parameter using the following Spice directive:

 

.STEP PARAM x_value start_value stop_value increment_value

 

·      Conversely, analysis can be repeated by first specifying a component with a parametric value x_value set between {x_value} and specifying a list of values for this parameter using the following Spice directive:

 

.STEP PARAM x_value LIST value_list

 

·      Any analysis can be repeated by specifying a range of values for a particular model parameter using the following parameter sweep command:

 

.STEP model_parameter start_value stop_value increment_value

 

·      A subcircuit described by SDL can be included with the circuit schematic. A subcircuit begins and ends as follows:

 

                             .SUBCKT subcircuit_name list_of_nodes

                SDL circuit description

.ENDS subcircuit_name

 

·      A subcircuit can be stored as a text file in a local directory and read into the Spice netlist by using the .include or .inc Spice directive command:

 

.INCLUDE file_path/file_name      or      .INC file_path/file_name

 

·      A call to a subcircuit in the SDL is to include an element description that begins with the letter X and is followed by the node connections and subcircuit name as follows:

 

Xname node_connections_to_subcircuit subcircuit_name {parameter_list}

 

·      In LTSpice, one often is working with a schematic entry; to access a subcircuit, the most direct way is to select an existing component that has the same number of terminals as the subcircuit component from the LTSpice component library, in much the same way as a resistor or capacitor is selected. Once selected and entered into the schematic windowpane and connect it to the rest of the circuit. Next, right click on the element to bring up the component attributes, as shown below:

 

 

First, ensure that the field of the Prefix attribute display an X.  Next, change the field named Value to the name of your subcircuit.   You can delete the values in the fields corresponding to Value2, SpiceLine and SpiceLine2, as these are not needed.

 

2.8 Bibliography

 

A. S. Sedra and K. C. Smith, Microelectronic Circuits, Oxford University Press, 1998-2015.

 

2.9 Problems

 

2.1.         Assuming a pseudo-ideal op amp model for each op amp (i.e., DC gain of 10⁶), determine, with the aid of Spice, the voltage gain v_o/v_i and input and output resistance of each of the circuits in Fig. P2.1.

 

2.2.         Design an inverting op amp circuit for which the gain is -4 V/V and the total resistance used is 100 kΩ.  Verify your design using Spice.

 

2.3.         Repeat Problem 2.1 for the case the op amps have a finite gain A=1000.

 

2.4.         A Miller integrator incorporates an ideal op amp, a resistor R of 100 kΩ and a capacitor C of 0.1 uF. Using the AC analysis capability of Spice, together with the ideal op amp represented by a high-gain VCVS, determine the following:

 

(a)   At what frequency are the input and output signals equal in amplitude?

 

(b)  At this frequency how does the phase of the output sinewave relate to that of the input?

 

(c)   If the frequency is lowered by a factor of 10 from that found in (a), by what factor does the output voltage change, and in what direction (smaller or larger)?

 

(d)  What is the phase relation between the input and output in situation (c)?

 

Confirm each of these situations by applying a 1-V peak sinewave at the appropriate frequency and compare the voltage waveform appearing at the output using the transient analysis of Spice.

 

Fig. P2.1

Fig. P2.5

 

2.5.         A Miller integrator whose input and output voltages are initially zero and whose time constant is 1 ms is driven by the signal shown in Fig. P2.5. Using Spice compute the output transient waveform that results. Repeat the above simulation with the input levels increased to ±2 V and the time constant raised to 2 ms. How does this output compare to that when the time constant is 1 ms?

 

2.6.         Consider a Miller integrator having a time constant of 1 ms, and whose output is initially zero, when fed with a string of pulses of 10-us duration and a 1 V amplitude rising from 0 V (see Fig. P2.6).  Use Spice to obtain a plot of the output voltage waveform. How many pulses are required for an output voltage change of 1 V?

 

Fig. P2.6

 

2.7.         In order to limit the low-frequency gain of a Miller integrator, a resistor is often shunted across the integrating capacitor.  Consider the case when the input resistor is 100 kΩ, the capacitor is 0.1 uF, and the shunt resistor is 10 M-Ω.

 

(a)    Use the AC analysis capability of Spice to compute the Bode plot of the magnitude response of the resulting circuit and contrast it with that of an ideal integrator (that is, without the shunt resistor). At what frequency does the circuit begin to behave less as an integrator and more as an amplifier?

 

(b)    Use the transient analysis capability of Spice to obtain a plot of the output voltage waveform resulting when an input pulse of 0.1 V height and 1 ms duration is applied. Consider the cases without and with the shunt resistor.

 

2.8.         A differentiator utilizes a pseudo-ideal op amp, a 10 kΩ resistor, and a 0.01 uF capacitor. Using the AC analysis command of Spice, determine the frequency f_o at which its input and output sinewave signals have equal magnitude. What is the output signal for a 1 V peak-to-peak sinewave input with frequency equal to 10f_o?

 

Fig. P2.9

 

2.9.         An op amp differentiator with a 1 ms time constant is driven by the rate-controlled step shown in Fig. P2.9. Initializing the output voltage at 0 V, compute the voltage time waveform that appears at the output using Spice over a time interval of at least 5 ms.

 

2.10.      A weighted summer circuit using a pseudo-ideal op amp has three inputs using 100 kW resistors and a feedback resistor of 50 k-Ω. A signal v₁ is connected to two of the inputs, while a signal v₂ is connected to the third. With the aid of Spice, determine the output voltage v_o if v₁=3 V and v₂=-3 V.

 

2.11.      Design an op amp circuit to provide an output v_o=-( 3 v₁ + v₂/2 ). Choose relatively low values of resistors but ones for which the input current (from each input signal source) does not exceed 0.1 mA for 2 V input signals. Verify all attributes of your design using Spice.

 

2.12.      In an instrumentation system, there is a need to take the difference between two signals, one being, v₁= 3 sin( 2p x 60 t)  +  0.01 sin( 2p x 1000 t) volts, and another, v₂ = 3 sin( 2p x 60 t)  -  0.01 sin( 2p x 1000 t)  volts. Design a difference amplifier that meets the above requirements using two op amps. In addition, amplify the resulting difference by a factor of 10. Verify your design using Spice by simulating the transient behavior of your circuit. Plot both the input and output signals. Model each op amp with a high-gain VCVS.

 

2.13.      It is required to connect a 10 V source with a source resistance of 100 k-Ω to a 1 k-Ω load. Find the voltage that will appear across the load if:

 

(a)   the source is connected directly across the load.

 

(b)  an op amp unity-gain buffer is inserted between the source and load.

 

In each case, find the load current and the current supplied by the source. Also, monitor the current supplied by the op amp. Assume that the op amp is pseudo-ideal with a DC gain of 10⁶.

 

2.14.      Consider the instrumentation amplifier of Fig. 2.15 with a common-mode input voltage of +5 V (dc) and a differential input signal of 10 mV peak, 1 kHz sinewave. Let R₁=1 k-Ω, R₂=0.5 M-Ω, and R₃=R₄=10 k-Ω. With the aid of Spice, plot the voltage waveform at each node in the circuit for at least 2 periods of the input signal.

 

Fig. P2.15

 

2.15.      For the negative impedance converter circuit of Fig. P2.15 with R=1 k-Ω and v_s =1 V, use Spice to determine the voltages across the load and at the output of the op amp, for load resistances of 0 Ω, 100 Ω, 1 kΩ and 2 k-Ω.

Fig. P2.16

 

2.16.      The circuit shown in Fig. P2.16 is intended to supply current to floating loads while making greatest possible use of the available power supplies. With a 1 V peak-to-peak, 1 Hz sinewave applied to its input, plot the voltage waveform appearing at nodes B and C. Also, plot v_o.  What is the voltage gain v_o / v_i?

 

2.17.      Measurements performed on an internally compensated op amp shows that at low frequencies its gain is 4.2 x 10⁴ V/V and has a 3-dB frequency located at 100 Hz. Create a small-signal equivalent circuit model of this op amp and verify using the AC frequency analysis of Spice that it satisfies the above measurements.

 

2.18.      A noninverting amplifier with a nominal gain of +20 V/V employs an op amp having a DC gain of 10⁴ and a unity-gain frequency of 10⁶ Hz. Model this behavior using an equivalent circuit, and with the aid of Spice, plot the magnitude response of the closed-loop amplifier and determine its 3-dB frequency f_3dB. What is the gain at 0.1 f_3dB and at 10 f_3dB?

 

2.19.      Consider a unity-gain follower utilizing an internally compensated op amp with f_t=1 MHz. Assume that the low frequency gain is 10⁶ V/V. Using Spice, determine the 3-dB frequency of the follower by plotting the magnitude response of the follower using the AC analysis command. At approximately what frequency is the gain of the follower 1% below its low frequency magnitude. What is the corresponding phase shift at this frequency? If the input to the follower is a 1 V step, determine the 10% to 90% rise time of the output voltage using the transient analysis command of Spice.

 

2.20.      Consider an inverting summer with two inputs V₁ and V₂ and with V_o = -(V₁ + V₂). With the aid of Spice, determine the 3-dB frequency of each of the gain functions V_o/V₁ and V_o/V₂ assuming that the small-signal behavior of the op amp is modeled after the 741 op amp. How do they compare with that predicted by theory? (Hint: In each case, the other input to the summer can be set to zero.)

 

2.21.      A Miller integrator uses a 100 kW input resistor and a feedback capacitor of 0.1 uF. Using Spice, compare the magnitude and phase response of this Miller integrator assuming that the op amp is: a) pseudo-ideal, and b) internally compensated with a dc gain of 10⁵ V/V and a 3 dB frequency of 10 Hz. For comparison purposes, its easiest to concatenate the two Spice files together and submit them together as one file to Spice.  In this way, the results of the two situations can be directly compared. What is the ``excess phase’’ that the nonideal integrator has at the unity-gain frequency of the (pseudo-)ideal integrator? Is the excess phase of the lag or lead type?

 

2.22.      A particular family of op amps has an internal structure that can be modeled as that in Fig. 2.25. Four separate designs are being considered that have the following small-signal parameters:

Create a Spice subcircuit that captures the above four circuit descriptions and then use it to plot the input-output voltage gain as a function of frequency. What is the DC gain, 3 dB and unity-gain frequencies for each op amp?

 

2.23.      Consider that the large-signal behavior of an internally compensated op amp can be modeled as that shown in Fig. 2.25. Assume that the resistor R has a 1 M-Ω value, capacitor C is 30 pF and the three control sources are described by the following mathematical expressions:

 

Create a Spice (LTSpice) subcircuit that captures the above behavior and verify that it indeed satisfies the given descriptions. Next, connect the op amp in a unity-gain configuration and apply a 5 V step input. Compute the expected output transient response and determine the positive-going slew-rate for this amplifier. How does this value compare with that predicted by theory?

 

2.24.      For the large-signal op amp described above in Problem 2.23, use Spice to compute the magnitude response for this amplifier as a function of frequency between 0.1 Hz and 100 MHz.  What is the corresponding DC gain, 3 dB and unity-gain frequencies?

 

2.25.      Consider an inverting amplifier configuration having a gain of -10. Using the large-signal op amp model described in Section 2.3, confirm that the highest frequency of a 15 V peak-to-peak sinewave that passes undistorted through the amplifier is 13.5 kHz. Do this by having Spice (LTSpice) compute the transient behavior of the amplifier subject to the 1.5 V peak-to-peak input sinewave of 13.4 kHz and compare this result to that when the frequency of the input signal is increased to 13.6 kHz.

 

2.26.      To demonstrate the many trade-offs that a designer faces when designing with op amps, consider investigating the limitations imposed on a noninverting amplifier having a nominal gain of 10 with an op amp that has a unity-gain bandwidth (f_t) of 2 MHz, a slew rate (SR) of 1 V/us and an output saturation voltage (V_omax) of 10 V. Model the op amp using the large-signal macromodel described in Section 2.3. Assume a sinewave input with peak amplitude V_i.

 

(a)    If V_i =0.5 V, what is the maximum frequency of the input signal that can be applied to this amplifier before the output signal shows visible distortions?

 

(b)    If the frequency of the input signal is 20 kHz, what is the maximum value of V_i before the output distorts?

 

(c)     If V_i =50 mV, what is the useful frequency range of operation?

 

(d)    If f=5 kHz, what is the useful input voltage range?

 

2.27.      An op amp with a DC gain of 10⁶ V/V and a CMRR of only 40 dB is used in a noninverting configuration with a closed-loop gain of 2. Model the behavior of this op amp using a Spice subcircuit consisting of several VCVSs. Plot the voltage waveform that appears at the output of the amplifier when an input signal wave of 1 kHz and 10 V peak-to-peak is applied to this amplifier configuration.

 

2.28.      A particular op amp, for which A₀=10⁴, R_iCM=10 M-Ω, and R_id = 10 kΩ, is connected in the noninverting configuration with a closed-loop gain of 10 (ideally).  Model the op amp with a VCVS, then, with the aid of Spice, determine the input resistance seen by the source for low frequencies?

 

2.29.      An op amp for which R_iCM = 50 M-Ω, R_id=10 kΩ, A₀=10⁴, and f_t=10⁶ Hz is used to design a noninverting amplifier with a nominal closed-loop gain of 10. Model the op amp with a single pole small-signal equivalent circuit model and create a Spice subcircuit for it before arranging the resistor feedback around it. With the aid of the AC analysis capability in Spice, apply a 1 V AC voltage signal to the amplifier input and plot the magnitude of the admittance seen by this source over a frequency interval of 0.1 Hz to 10⁷ Hz.

 

2.30.      An inverting amplifier for which R₁=10 kΩ and R₂=100 kΩ is constructed with an op amp whose open-loop output resistance is 1 kΩ, whose dc gain is 10⁴, and whose 3-dB frequency is 100 Hz. Evaluate the magnitude of the output impedance of the closed loop amplifier over a frequency interval of 0.01 Hz to 10⁷ Hz. Select a logarithmic sweep of the input signal frequency.

 

2.31.      A noninverting amplifier with a gain of 100 uses an op amp having an input offset voltage of ±2 mV. Assume that the rest of the op amp can be modeled as a high-gain VCVS. If a 10-mV peak sinewave of 1 Hz frequency is applied to the input of the amplifier, observe the voltage waveform that appears at the amplifier output using Spice.

Fig. P2.32

 

2.32.      Consider the differential amplifier circuit in Fig. P2.32. Let R₁=R₃=10 kΩ and R₂=R₄=1 M-Ω. If the op amp has V_OS = 3 mV, I_B=0.2 uA, and I_OS=50 nA, determine, with the help of Spice, the dc offset voltage that appears at the amplifiers output. Assume that the rest of the op amp is pseudo-ideal (i.e., modeled as a high-gain VCVS).

Fig. P2.33

 

2.33.      The circuit shown in Fig. P2.33 uses an op amp that has a ±5 V offset. Assume that the op amp is pseudo-ideal except for the dc offset. Determine the output offset voltage using Spice. What does the output offset become with the input ac coupled through a 1 uF capacitor? If, instead, the 1 kΩ resistor is capacitively coupled to ground, what does the output offset become?

 

2.34.      An op amp is connected in a closed loop with gain of +100 utilizing a feedback resistor of 1 M-Ω. With the aid of Spice, answer the following:

 

(a)   If the input bias current is 100 nA and everything else about the op amp is assumed ideal, what output voltage results with the input grounded?

 

(b)   If the input offset voltage is ±1 mV, and the input bias current as in (a), what is the largest possible output that can be observed with the input grounded?

 

(c)   If bias current compensation is used, what is the value of the required resistor? Verify that this indeed reduces the output offset voltage.